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VLSI test principles and architectures = design for testability /

Record Type:	Electronic resources : Monograph/item
Title/Author:	VLSI test principles and architectures/ edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen.{me_controlnum}
Reminder of title:	design for testability /
other author:	Wang, Laung-Terng.
Published:	Amsterdam ;Elsevier Morgan Kaufmann Publishers, : c2006.,
Description:	1 online resource (xxx, 777 p.) :ill.
[NT 15003449]:	Chapter 1 Introduction -- Chapter 2 Design for Testability -- Chapter 3 Logic and Fault Simulation -- Chapter 4 Test Generation -- Chapter 5 Logic Built-In Self-Test -- Chapter 6 Test Compression -- Chapter 7 Logic Diagnosis -- Chapter 8 Memory Testing and Built-In Self-Test -- Chapter 9 Memory Diagnosis and Built-In Self-Repair -- Chapter 10 Boundary Scan and Core-Based Testing -- Chapter 11 Analog and Mixed-Signal Testing -- Chapter 12 Test Technology Trends in the Nanometer Age.
Subject:	Integrated circuits - Very large scale integration -
Online resource:	http://www.sciencedirect.com/science/book/9780123705976
ISBN:	9780123705976

VLSI test principles and architectures = design for testability /
VLSI test principles and architecturesdesign for testability /[electronic resource] :edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen.{me_controlnum} - Amsterdam ;Elsevier Morgan Kaufmann Publishers,c2006. - 1 online resource (xxx, 777 p.) :ill. - The Morgan Kaufmann series in systems on silicon. - Morgan Kaufmann series in systems on silicon..

Includes bibliographical references and index.

Chapter 1 Introduction -- Chapter 2 Design for Testability -- Chapter 3 Logic and Fault Simulation -- Chapter 4 Test Generation -- Chapter 5 Logic Built-In Self-Test -- Chapter 6 Test Compression -- Chapter 7 Logic Diagnosis -- Chapter 8 Memory Testing and Built-In Self-Test -- Chapter 9 Memory Diagnosis and Built-In Self-Repair -- Chapter 10 Boundary Scan and Core-Based Testing -- Chapter 11 Analog and Mixed-Signal Testing -- Chapter 12 Test Technology Trends in the Nanometer Age.

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

ISBN: 9780123705976

Source: 132281:132389Elsevier Science & Technologyhttp://www.sciencedirect.comSubjects--Topical Terms:

629092
Integrated circuits
--Very large scale integrationIndex Terms--Genre/Form:

542853
Electronic books.

LC Class. No.: TK7874.75 / .V587 2006eb

Dewey Class. No.: 621.39/5

VLSI test principles and architectures = design for testability /
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505 0 $a Chapter 1 Introduction -- Chapter 2 Design for Testability -- Chapter 3 Logic and Fault Simulation -- Chapter 4 Test Generation -- Chapter 5 Logic Built-In Self-Test -- Chapter 6 Test Compression -- Chapter 7 Logic Diagnosis -- Chapter 8 Memory Testing and Built-In Self-Test -- Chapter 9 Memory Diagnosis and Built-In Self-Repair -- Chapter 10 Boundary Scan and Core-Based Testing -- Chapter 11 Analog and Mixed-Signal Testing -- Chapter 12 Test Technology Trends in the Nanometer Age.
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