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VLSI test principles and architectures = design for testability /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	VLSI test principles and architectures/ edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen.{me_controlnum}
其他題名:	design for testability /
其他作者:	Wang, Laung-Terng.
出版者:	Amsterdam ;Elsevier Morgan Kaufmann Publishers, : c2006.,
面頁冊數:	1 online resource (xxx, 777 p.) :ill.
內容註:	Chapter 1 Introduction -- Chapter 2 Design for Testability -- Chapter 3 Logic and Fault Simulation -- Chapter 4 Test Generation -- Chapter 5 Logic Built-In Self-Test -- Chapter 6 Test Compression -- Chapter 7 Logic Diagnosis -- Chapter 8 Memory Testing and Built-In Self-Test -- Chapter 9 Memory Diagnosis and Built-In Self-Repair -- Chapter 10 Boundary Scan and Core-Based Testing -- Chapter 11 Analog and Mixed-Signal Testing -- Chapter 12 Test Technology Trends in the Nanometer Age.
標題:	Integrated circuits - Very large scale integration -
電子資源:	http://www.sciencedirect.com/science/book/9780123705976
ISBN:	9780123705976

VLSI test principles and architectures = design for testability /
VLSI test principles and architecturesdesign for testability /[electronic resource] :edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen.{me_controlnum} - Amsterdam ;Elsevier Morgan Kaufmann Publishers,c2006. - 1 online resource (xxx, 777 p.) :ill. - The Morgan Kaufmann series in systems on silicon. - Morgan Kaufmann series in systems on silicon..

Includes bibliographical references and index.

Chapter 1 Introduction -- Chapter 2 Design for Testability -- Chapter 3 Logic and Fault Simulation -- Chapter 4 Test Generation -- Chapter 5 Logic Built-In Self-Test -- Chapter 6 Test Compression -- Chapter 7 Logic Diagnosis -- Chapter 8 Memory Testing and Built-In Self-Test -- Chapter 9 Memory Diagnosis and Built-In Self-Repair -- Chapter 10 Boundary Scan and Core-Based Testing -- Chapter 11 Analog and Mixed-Signal Testing -- Chapter 12 Test Technology Trends in the Nanometer Age.

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

ISBN: 9780123705976

Source: 132281:132389Elsevier Science & Technologyhttp://www.sciencedirect.comSubjects--Topical Terms:

629092
Integrated circuits
--Very large scale integrationIndex Terms--Genre/Form:

542853
Electronic books.

LC Class. No.: TK7874.75 / .V587 2006eb

Dewey Class. No.: 621.39/5

VLSI test principles and architectures = design for testability /
LDR:03238cmm 2200505Ia 4500 001 1325704
005 20120813091434.0
006 m d
007 cr cn|||||||||
008 130122s2006 ne a ob 001 0 eng d
019 $a 123441360 $a 154703466 $a 299750751 $a 434023516 $a 441775657 $a 648178245 $a 772045718
020 $a 9780123705976
020 $a 0123705975
020 $a 9780080474793 (electronic bk.)
020 $a 0080474799 (electronic bk.)
020 $a 6610966842 (electronic bk.)
020 $a 9786610966844 (electronic bk.)
029 1 $a NZ1 $b 12434945
029 1 $a AU@ $b 000043319312
029 1 $a DEBSZ $b 355395088
029 1 $a DEBBG $b BV039832118
029 1 $a HEBIS $b 291468322
035 $a ocn162573568
037 $a 132281:132389 $b Elsevier Science & Technology $n http://www.sciencedirect.com
040 $a OPELS $b eng $c OPELS $d OCLCG $d OCLCQ $d N$T $d EBLCP $d MERUC $d E7B $d IDEBK $d UMI $d CEF $d NHM $d DEBSZ $d KNOVL
049 $a NTYA
050 4 $a TK7874.75 $b .V587 2006eb
072 7 $a TEC $x 008050 $2 bisacsh
072 7 $a TEC $x 008030 $2 bisacsh
072 7 $a COM $x 036000 $2 bisacsh
082 0 4 $a 621.39/5 $2 22
084 $a ZN 4030 $2 rvk
084 $a ZN 4950 $2 rvk
084 $a ZN 4952 $2 rvk
245 0 0 $a VLSI test principles and architectures $h [electronic resource] : $b design for testability / $c edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen.{me_controlnum}
260 $a Amsterdam ; $a Boston : $b Elsevier Morgan Kaufmann Publishers, $c c2006.
300 $a 1 online resource (xxx, 777 p.) : $b ill.
490 1 $a The Morgan Kaufmann series in systems on silicon
504 $a Includes bibliographical references and index.
505 0 $a Chapter 1 Introduction -- Chapter 2 Design for Testability -- Chapter 3 Logic and Fault Simulation -- Chapter 4 Test Generation -- Chapter 5 Logic Built-In Self-Test -- Chapter 6 Test Compression -- Chapter 7 Logic Diagnosis -- Chapter 8 Memory Testing and Built-In Self-Test -- Chapter 9 Memory Diagnosis and Built-In Self-Repair -- Chapter 10 Boundary Scan and Core-Based Testing -- Chapter 11 Analog and Mixed-Signal Testing -- Chapter 12 Test Technology Trends in the Nanometer Age.
520 $a This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.
588 $a Description based on print version record.
650 0 $a Integrated circuits $x Very large scale integration $x Testing. $3 629092
650 0 $a Integrated circuits $x Very large scale integration $x Design. $3 629093
650 6 $a Circuits int�egr�es �a tr�es grande �echelle $x Essais. $3 1613664
650 6 $a Circuits int�egr�es �a tr�es grande �echelle $x Conception et construction. $3 1613665
650 7 $a TECHNOLOGY & ENGINEERING $x Electronics $x Circuits $x VLSI & ULSI. $2 bisacsh $3 1613666
650 7 $a TECHNOLOGY & ENGINEERING $x Electronics $x Circuits $x Logic. $2 bisacsh $3 1613667
650 7 $a COMPUTERS $x Logic Design. $2 bisacsh $3 1613668
650 7 $a Circuitos integrados vlsi. $2 larpcal $3 1613669
650 7 $a Integrated circuits / Very large scale integration / Testing. $2 blmsh $3 1613670
650 7 $a Integrated circuits / Very large scale integration / Design. $2 blmsh $3 1613671
650 0 7 $a Testen. $2 gtt $3 1000449
650 0 7 $a VLSI. $2 swd $3 1613672
655 4 $a Electronic books. $2 lcsh $3 542853
700 1 $a Wang, Laung-Terng. $3 629088
700 1 $a Wu, Cheng-Wen, $c EE Ph. D. $3 983122
700 1 $a Wen, Xiaoqing. $3 983123
776 0 8 $i Print version: $t VLSI test principles and architectures. $d Amsterdam ; Boston : Elsevier Morgan Kaufmann Publishers, c2006 $z 0123705975 $z 9780123705976 $w (DLC) 2006006869 $w (OCoLC)64624834
830 0 $a Morgan Kaufmann series in systems on silicon. $3 1068550
856 4 0 $3 ScienceDirect $u http://www.sciencedirect.com/science/book/9780123705976
938 $a ebrary $b EBRY $n ebr10169928
938 $a Ingram Digital eBook Collection $b IDEB $n 96684