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Algorithmic Optimization of First Co...

Chamarthi, Ramachandra Vikas.

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Algorithmic Optimization of First Convolution Layer in Cnns for Hardware Accelerator Design.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Algorithmic Optimization of First Convolution Layer in Cnns for Hardware Accelerator Design./
Author:	Chamarthi, Ramachandra Vikas.
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2019,
Description:	66 p.
Notes:	Source: Masters Abstracts International, Volume: 80-10.
Contained By:	Masters Abstracts International80-10.
Subject:	Computer Engineering. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=13806248
ISBN:	9781392029664

Algorithmic Optimization of First Convolution Layer in Cnns for Hardware Accelerator Design.
Chamarthi, Ramachandra Vikas.

Algorithmic Optimization of First Convolution Layer in Cnns for Hardware Accelerator Design. - Ann Arbor : ProQuest Dissertations & Theses, 2019 - 66 p.

Source: Masters Abstracts International, Volume: 80-10.

Thesis (M.S.)--The University of North Carolina at Charlotte, 2019.

This item must not be sold to any third party vendors.

This thesis proposes "1D Convolution replacement layer", a novel optimization for first convolution layer in CNN. This optimization enables edge friendly streaming accelerator design with a minimum drop in accuracy. This optimization reduces the number of convolution parameters in the first convolution layers of CNN, reducing the number of multiplications performed in convolution operation. In CNNs first convolution is the most memory and compute intensive as the first layer operates on input. In a streaming accelerator design, the first layer operates on streaming data, the complexity of operations and memory demand of the first layer will proportionally affect the latency of complete accelerator design. Using 1D Convolution replacement in a CNN on a N x N convolution layer after 1D replacement number of operations in each convolution window gets reduced by N times. To show the effect of 1D convolution in accelerators, streaming accelerator design for SqueezeNet is compared with 1D-SqueezeNet, SqueezeNet with 1D convolution replacement in the first layer is discussed. 1D replacement enabled edge friendly design reducing the dynamic power consumption by 7.3X, with 0.6\\% drop in accuracy in SqueezeNet real-time edge accelerator.

ISBN: 9781392029664Subjects--Topical Terms:

1567821
Computer Engineering.

Algorithmic Optimization of First Convolution Layer in Cnns for Hardware Accelerator Design.
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100 1 $a Chamarthi, Ramachandra Vikas. $3 3435166
245 1 0 $a Algorithmic Optimization of First Convolution Layer in Cnns for Hardware Accelerator Design.
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300 $a 66 p.
500 $a Source: Masters Abstracts International, Volume: 80-10.
500 $a Publisher info.: Dissertation/Thesis.
500 $a Advisor: Tabkhi, Hamed.
502 $a Thesis (M.S.)--The University of North Carolina at Charlotte, 2019.
506 $a This item must not be sold to any third party vendors.
520 $a This thesis proposes "1D Convolution replacement layer", a novel optimization for first convolution layer in CNN. This optimization enables edge friendly streaming accelerator design with a minimum drop in accuracy. This optimization reduces the number of convolution parameters in the first convolution layers of CNN, reducing the number of multiplications performed in convolution operation. In CNNs first convolution is the most memory and compute intensive as the first layer operates on input. In a streaming accelerator design, the first layer operates on streaming data, the complexity of operations and memory demand of the first layer will proportionally affect the latency of complete accelerator design. Using 1D Convolution replacement in a CNN on a N x N convolution layer after 1D replacement number of operations in each convolution window gets reduced by N times. To show the effect of 1D convolution in accelerators, streaming accelerator design for SqueezeNet is compared with 1D-SqueezeNet, SqueezeNet with 1D convolution replacement in the first layer is discussed. 1D replacement enabled edge friendly design reducing the dynamic power consumption by 7.3X, with 0.6\\% drop in accuracy in SqueezeNet real-time edge accelerator.
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710 2 $a The University of North Carolina at Charlotte. $b Electrical Engineering. $3 3170016
773 0 $t Masters Abstracts International $g 80-10.
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856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=13806248