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Design of Low OSR, High Precision An...

Rajaee, Omid.

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Design of Low OSR, High Precision Analog-to-Digital Converters.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Design of Low OSR, High Precision Analog-to-Digital Converters./
作者:	Rajaee, Omid.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2010,
面頁冊數:	131 p.
附註:	Source: Dissertation Abstracts International, Volume: 72-06, Section: B, page: 3633.
Contained By:	Dissertation Abstracts International72-06B.
標題:	Electrical engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3452574
ISBN:	9781124596099

Design of Low OSR, High Precision Analog-to-Digital Converters.
Rajaee, Omid.

Design of Low OSR, High Precision Analog-to-Digital Converters. - Ann Arbor : ProQuest Dissertations & Theses, 2010 - 131 p.

Source: Dissertation Abstracts International, Volume: 72-06, Section: B, page: 3633.

Thesis (Ph.D.)--Oregon State University, 2010.

This item is not available from ProQuest Dissertations & Theses.

Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well-known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures.

ISBN: 9781124596099Subjects--Topical Terms:

649834
Electrical engineering.

Design of Low OSR, High Precision Analog-to-Digital Converters.
LDR:02626nmm a2200301 4500 001 2157501
005 20180605073452.5
008 190424s2010 ||||||||||||||||| ||eng d
020 $a 9781124596099
035 $a (MiAaPQ)AAI3452574
035 $a AAI3452574
040 $a MiAaPQ $c MiAaPQ
100 1 $a Rajaee, Omid. $3 3345311
245 1 0 $a Design of Low OSR, High Precision Analog-to-Digital Converters.
260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2010
300 $a 131 p.
500 $a Source: Dissertation Abstracts International, Volume: 72-06, Section: B, page: 3633.
500 $a Adviser: Un-Ku Moon.
502 $a Thesis (Ph.D.)--Oregon State University, 2010.
506 $a This item is not available from ProQuest Dissertations & Theses.
520 $a Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well-known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures.
520 $a In this thesis, different combinations of delta-sigma and pipelined ADCs are explored and new techniques for designing oversampled ADCs are proposed. A Hybrid Delta-Sigma/Pipelined (HDSP) ADC is presented. This ADC uses a pipelined ADC as the quantizer of a single-loop delta-sigma modulator and benefits from the aggressive quantization of the pipelined quantizer at low OSRs. A Noise-Shaped Pipelined ADC is proposed which exploits a delta-sigma modulator as the sub-ADC of a pipeline stage to reduce the sensitivity to the analog imperfection. Three prototype ADCs were fabricated in 0.18microm CMOS technology to verify the effectiveness of the proposed techniques. The performance of these architectures is among the best reported for high bandwidth oversampled ADCs.
590 $a School code: 0172.
650 4 $a Electrical engineering. $3 649834
690 $a 0544
710 2 $a Oregon State University. $3 625720
773 0 $t Dissertation Abstracts International $g 72-06B.
790 $a 0172
791 $a Ph.D.
792 $a 2010
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3452574