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Performance enhancement of pipeline ...

Li, Ting.

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Performance enhancement of pipeline ADCs.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Performance enhancement of pipeline ADCs./
作者:	Li, Ting.
面頁冊數:	170 p.
附註:	Source: Dissertation Abstracts International, Volume: 76-02(E), Section: B.
Contained By:	Dissertation Abstracts International76-02B(E).
標題:	Electrical engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3640277
ISBN:	9781321256000

Performance enhancement of pipeline ADCs.
Li, Ting.

Performance enhancement of pipeline ADCs. - 170 p.

Source: Dissertation Abstracts International, Volume: 76-02(E), Section: B.

Thesis (Ph.D.)--North Dakota State University, 2014.

The pipeline ADC is mainstream architecture in wireless communication and digital consumer products because of its speed, resolution, dynamic performance, and power consumption. However, there are three areas of concern with the pipeline analog-to-digital converter (ADC): power consumption, accuracy, and convergence speed of the digital calibration. The traditional pipeline ADC includes a dedicated front-end sample-and-hold amplifier (SHA), which consumes a significant amount of power. This research presents a novel configuration of the front-end stage with a sample-and-hold function for a SHA-less architecture. In addition, the multi-bit front-end has multiple benefits. Interestingly, if one additional bit is resolved in the front-end stage, then the comparator offset correction ability of this stage is reduced by half. To address this problem, this research presents a novel domain-extended digital error correction algorithm to increase the comparator offset correction ability. In order to improve accuracy, a combination of techniques are used: communicated feedback-capacitor switching (CFCS), gain boost amplifiers, and low noise dynamic comparators. Here, the ADC uses the above mentioned techniques and is fabricated with AMIS 0.5 microm CMOS. The ADC, with an active area of 4.5 mm2, consumes 264 mW when a 32 MHz input is at 75-MS/s sample rate.

ISBN: 9781321256000Subjects--Topical Terms:

649834
Electrical engineering.

Performance enhancement of pipeline ADCs.
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245 1 0 $a Performance enhancement of pipeline ADCs.
300 $a 170 p.
500 $a Source: Dissertation Abstracts International, Volume: 76-02(E), Section: B.
500 $a Adviser: Chao You.
502 $a Thesis (Ph.D.)--North Dakota State University, 2014.
520 $a The pipeline ADC is mainstream architecture in wireless communication and digital consumer products because of its speed, resolution, dynamic performance, and power consumption. However, there are three areas of concern with the pipeline analog-to-digital converter (ADC): power consumption, accuracy, and convergence speed of the digital calibration. The traditional pipeline ADC includes a dedicated front-end sample-and-hold amplifier (SHA), which consumes a significant amount of power. This research presents a novel configuration of the front-end stage with a sample-and-hold function for a SHA-less architecture. In addition, the multi-bit front-end has multiple benefits. Interestingly, if one additional bit is resolved in the front-end stage, then the comparator offset correction ability of this stage is reduced by half. To address this problem, this research presents a novel domain-extended digital error correction algorithm to increase the comparator offset correction ability. In order to improve accuracy, a combination of techniques are used: communicated feedback-capacitor switching (CFCS), gain boost amplifiers, and low noise dynamic comparators. Here, the ADC uses the above mentioned techniques and is fabricated with AMIS 0.5 microm CMOS. The ADC, with an active area of 4.5 mm2, consumes 264 mW when a 32 MHz input is at 75-MS/s sample rate.
520 $a The third area of concern is convergence time, which determines the quality of the digital calibration. The high resolution ADC can be achieved without calibration. Therefore, in order for a digital calibration to be useful, it should minimize the analog circuits and have a reasonable convergence time. The reduced accuracy due to minimized analog circuits can be complemented by the digital calibration. Therefore, the convergence time determines the quality of the digital calibration. In this research a new domain-extended dither-based algorithm increases the convergence speed. Moreover, the novel variable-amplitude domain-extended dither-based algorithm further increases the convergence speed. Matlab simulations illustrate these improvements.
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