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Software tools for modeling and simu...

Zhu, Xinping.

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Software tools for modeling and simulation of on-chip communication architectures.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Software tools for modeling and simulation of on-chip communication architectures./
作者:	Zhu, Xinping.
面頁冊數:	161 p.
附註:	Source: Dissertation Abstracts International, Volume: 66-01, Section: B, page: 0473.
Contained By:	Dissertation Abstracts International66-01B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3162776
ISBN:	049696531X

Software tools for modeling and simulation of on-chip communication architectures.
Zhu, Xinping.

Software tools for modeling and simulation of on-chip communication architectures. - 161 p.

Source: Dissertation Abstracts International, Volume: 66-01, Section: B, page: 0473.

Thesis (Ph.D.)--Princeton University, 2005.

In multiprocessor based systems-on-chips (SoCs), optimizing the communication architecture is often as important as, if not more than, optimizing the computation architecture. Designers need to make important choices related to the on-chip communication architectures, i.e. Network-on-Chips (NoCs). These choices are often not self-evident. Designers need to understand the interplay between the application, the Processor Element (PE) architecture and the NoC to make the right decisions. At the same time, there is a tremendous pressure on designers to accelerate the "time-to-market" of their design without sacrificing the design quality. Achieving this requires a set of design automation tools which can model, simulate and verify the components of the system design before the silicon is available. Thus, a major challenge in designing the NoC is to build an efficient and accurate model for simulation and performance evaluation.

ISBN: 049696531XSubjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Software tools for modeling and simulation of on-chip communication architectures.
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245 1 0 $a Software tools for modeling and simulation of on-chip communication architectures.
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502 $a Thesis (Ph.D.)--Princeton University, 2005.
520 $a In multiprocessor based systems-on-chips (SoCs), optimizing the communication architecture is often as important as, if not more than, optimizing the computation architecture. Designers need to make important choices related to the on-chip communication architectures, i.e. Network-on-Chips (NoCs). These choices are often not self-evident. Designers need to understand the interplay between the application, the Processor Element (PE) architecture and the NoC to make the right decisions. At the same time, there is a tremendous pressure on designers to accelerate the "time-to-market" of their design without sacrificing the design quality. Achieving this requires a set of design automation tools which can model, simulate and verify the components of the system design before the silicon is available. Thus, a major challenge in designing the NoC is to build an efficient and accurate model for simulation and performance evaluation.
520 $a The contributions of this dissertation are twofold. First, a new methodology based on modular design and object-oriented modeling techniques is proposed. This methodology is based on an object-oriented class hierarchy for the NoC and a dedicated NoC module library organized according to this hierarchical structure. Second, a retargetable simulation framework is developed where SoC designs can be constructed easily and evaluated efficiently and faithfully. The modeling and simulation platform is based on a formal concurrency model, the Operation State Machine (OSM). The NoC models are constructed faithfully by explicitly modeling both the operation concurrency and the microarchitecture concurrency. Coupled with existing PE models, this framework is capable of synthesizing a multiprocessor cycle-accurate SoC simulator from a system-level description. The case studies include a router-based packet-switching on-chip communication network and an industry-standard on-chip bus architecture. Experiment results show that this framework can significantly reduce the design turnaround time and improve design reuse in the early stages of SoC design.
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