東華大學圖書館 |

語系: 繁體中文

說明(常見問題)

回圖書館首頁

手機版館藏查詢

登入

回首頁 到查詢結果 [ null ]

切換: 標籤 | MARC模式 | ISBD

Low-power techniques for supply-nois...

Arakali, Abhijith.

FindBook

Google Book

Amazon

博客來

Low-power techniques for supply-noise mitigation in phase-locked loops.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Low-power techniques for supply-noise mitigation in phase-locked loops./
作者:	Arakali, Abhijith.
面頁冊數:	117 p.
附註:	Source: Dissertation Abstracts International, Volume: 71-03, Section: B, page: 1908.
Contained By:	Dissertation Abstracts International71-03B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3401172
ISBN:	9781109682977

Low-power techniques for supply-noise mitigation in phase-locked loops.
Arakali, Abhijith.

Low-power techniques for supply-noise mitigation in phase-locked loops. - 117 p.

Source: Dissertation Abstracts International, Volume: 71-03, Section: B, page: 1908.

Thesis (Ph.D.)--Oregon State University, 2010.

Modern day digital systems employ frequency synthesizers to provide a common clock to the system. They are undergoing large scale integration due to which, mitigation of the effect of noise on power supply has become a major design consideration in clocking circuits. Rapid scaling of CMOS technology mandates the design of frequency synthesizers in a low supply voltage environment. Maintaining the supply noise immunity of clocking circuits in low-voltage processes is particularly challenging.

ISBN: 9781109682977Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Low-power techniques for supply-noise mitigation in phase-locked loops.
LDR:03400nam 2200289 4500 001 1399807
005 20110930095834.5
008 130515s2010 ||||||||||||||||| ||eng d
020 $a 9781109682977
035 $a (UMI)AAI3401172
035 $a AAI3401172
040 $a UMI $c UMI
100 1 $a Arakali, Abhijith. $3 1678819
245 1 0 $a Low-power techniques for supply-noise mitigation in phase-locked loops.
300 $a 117 p.
500 $a Source: Dissertation Abstracts International, Volume: 71-03, Section: B, page: 1908.
500 $a Adviser: Pavan Kumar Hanumolu.
502 $a Thesis (Ph.D.)--Oregon State University, 2010.
520 $a Modern day digital systems employ frequency synthesizers to provide a common clock to the system. They are undergoing large scale integration due to which, mitigation of the effect of noise on power supply has become a major design consideration in clocking circuits. Rapid scaling of CMOS technology mandates the design of frequency synthesizers in a low supply voltage environment. Maintaining the supply noise immunity of clocking circuits in low-voltage processes is particularly challenging.
520 $a In this thesis, techniques to mitigate the effect of supply-noise in frequency synthesizers are explored. The ring-oscillator based frequency synthesizer is an important part of many clocking circuits. They are used in various digital communication systems and as a building block in high speed signalling systems. They suffer from high sensitivity to power supply noise thereby requiring careful design considerations to improve its supply noise immunity. In light of the above, an attempt has been made to improve the immunity of the ring-oscillator based frequency synthesizer to noise on the supply voltage. The effect of noise on the supplies of other building blocks of a frequency synthesizer, though not as pronounced as that of noise on the ring-oscillator supply, is quite significant. Analysis of effect of power supply noise on various building blocks of the frequency synthesizer are presented. Also, techniques to effectively reduce the effect of power supply noise on the performance of the frequency synthesizer are presented. Measured results from proof-of-concept ICs are presented to illustrate the effectiveness of the proposed techniques.
520 $a Clock and data recovery (CDR) circuits which utilize ring-oscillators are also highly sensitive to power supply noise. Measurement of CDR jitter tolerance without the use of expensive equipment is another challenge involved in the design of CDRs. An on-chip jitter tolerance measurement technique is presented wherein, a phase averaging dual loop CDR architecture is used which comprises of a phase-locked loop (PLL) inside the CDR loop. Previously proposed idea of using oversampling in this architecture has proven to considerably reduce power consumption in this CDR architecture. In this thesis, an attempt has been made to further reduce the power consumption. The PLL in this CDR architecture utilizes the proposed supply regulated PLL architecture in order to minimize the bit-error rate (BER) of the CDR due to power supply noise.
590 $a School code: 0172.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 $a Oregon State University. $3 625720
773 0 $t Dissertation Abstracts International $g 71-03B.
790 1 0 $a Hanumolu, Pavan Kumar, $e advisor
790 $a 0172
791 $a Ph.D.
792 $a 2010
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3401172